LDO_VQFN_Lab
Kepa Odriozola mail
This project features a power supply circuit centered on the AP7361C LDO regulator. It converts a 2.2V to 6.0V input into a stable 3.3V output with ±1% accuracy. To manage power, SW1 (POWER ON) and SW2 (RESET) pulses are debounced by a 74LVC2G14 inverter. A 74AHCT32 OR gate creates a latch, while a 74HCT08 AND gate acts as a kill switch to maintain Enable signal only if the latch is active and RESET is not pressed. 2 green LEDs (D1, D2) provide visual feedback status for the +5V and +3V3 rails.
Version
1.0Licenses
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Project Type
Electronics
